Interleaved Pixel Lookup

figure

This project tries to parallelize pixel lookup operations in embedded computer vision hardware. Implementation of pixel lookup, a conversion between geometry to pixel data, is a design bottleneck for embedded hardware. It usually requires random accesses that take large portion of hardware cost and consume more energy, while it is difficult to increase its throughput. For efficient implementation, we focus on interleaving, a technique to parallelize memory operations successfully utilized in graphics hardwares. An FPGA implementation of Lucas-Kanade, one of the most basic image registration algorithms, showed that interleaving contributes to 16x times larger throughput than straightforward configuration with a single port memory without major increase in hardware cost.